Multi-Chip Package

ABSTRACT

A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.

TECHNICAL FIELD

This specification refers to embodiments of a package enclosing aplurality of power semiconductor chips and to embodiments of system forsupplying a load current to a load, said system including a packageenclosing a plurality of power semiconductor chips. In particular, thisspecification refers to embodiments of a Surface-Mount Device (SMD)package with Top Side Cooling, said package enclosing a plurality ofpower semiconductor chips, and to embodiments of a system including suchpackage.

BACKGROUND

Many functions of modern devices in automotive, consumer and industrialapplications, such as converting electrical energy and driving anelectric motor or an electric machine, rely on power semiconductordevices.

For example, Insulated Gate Bipolar Transistors (IGBTs), Metal OxideSemiconductor Field Effect Transistors (MOSFETs) and diodes, to name afew, have been used for various applications including, but not limitedto switches in power supplies and power converters.

A power semiconductor device usually comprises one or more powersemiconductor chips, each configured to conduct a load current along aload current path between two load terminals of the respective chip.Further, the load current path may be controlled, e.g., by means of aninsulated electrode, sometimes referred to as gate electrode. Forexample, upon receiving a corresponding control signal from, e.g., adriver, the control electrode may set the power semiconductor chip inone of a conducting state and a blocking state.

After the power semiconductor chip has been manufactured, it is usuallyinstalled within in a package, e.g., in a manner that allows the packagewith the chip(s) to be arranged within an application, e.g., in a powerconverter or power supply system, e.g., such that the chip(s) may becoupled, as part of the package, to a carrier, e.g., a printed circuitboard (PCB).

To this end, a technology commonly referred to as surface-mounttechnology (SMT) is known, wherein this notion may generally refer toproducing electronic circuits in which the components are mounted orplaced directly onto the surface of a PCB. Such a component is hencereferred to as surface-mount-device (SMD) component.

Another mounting configuration is the so-called through-hole technology,e.g., a construction method of fitting components with wire leads intoholes in a circuit board.

Generally, an SMD component can be smaller than its through-holecounterpart. Nevertheless, both technologies are still used nowadays.

A package may have short pins or leads of various styles, flat contacts(also known as “terminal pads”), a matrix of solder balls (e.g., aso-called Ball Grid Array (BGA)), and/or terminations on the packagebody of the component.

Exemplary configurations of an SMD package are known from documents DE10 2015 101 674 A1 and DE 10 2015 120 396 A1.

Each of these known SMD packages encloses a power semiconductor chip andhas a package body with a package top side, a package footprint side andpackage sidewalls, wherein the package sidewalls extend from the packagefootprint side to the package top side. The chip has a first loadterminal and a second load terminal and is configured to block ablocking voltage applied between said load terminals.

The above identified known SMD packages each further comprise a leadframe structure for electrically and mechanically coupling the packageto a support with the package footprint side facing to the support. Thelead frame structure comprises outside terminals extending out of thepackage sidewall and electrically connected with the first load terminalof the chip. Further, each of the packages comprise a top layer arrangedat the package top side and being electrically connected with the secondload terminal of the chip.

Accordingly, each of these SMD packages known from documents DE 10 2015101 674 A1 and DE 10 2015 120 396 A1 may exhibit a package top side thatfaces away from the support and that is equipped with a top layer towhich a heat dissipation device, e.g., a heat sink, may be mounted.Thereby, heat can be removed away from the package that encloses thechip. Such kind of packages may hence be referred to as a SMD-Top SideCooling (SMD-TSC) packages.

The primary function of the components fulfilling heat dissipation is toremove heat away from the package body. To this end, it is for exampleknown to couple a heat sink to the top layer, e.g., by means of anintermediate component, such as a heat spreader. The heat sink may beelectrically insulated from the top layer.

Of course, the dimension and/or configuration of the means fordissipating heat of the package correlate with the heat generated by thechip(s) that operate(s) within the package, i.e., the losses generatedby the chip(s) during operation. For example, such losses occur duringswitching event (so-called switching losses) and during load currentconduction (so-called on-state losses or static losses). Losses that mayoccur during constant off-state (blocking state) of the chip(s) arerather significantly lower than the switching losses and the on-statelosses.

The configuration of the package (and/or the heat dissipation device(s)coupled thereto) typically correlate with the amount of power lossesgenerated within the package body, i.e., by the one or more chipsincluded therein. The higher the losses, the larger/the more complex thepackage (and/or the heat dissipation device(s) coupled thereto) has tobe designed.

Low on-state losses or static losses can be achieved by connecting andoperating several power semiconductor chips in parallel, because thetotal on-state resistance of the parallel connected chips is reduced ascompared to an individual on-state resistance of one chip.

SUMMARY

Certain aspects of the present specification are related to embodimentsof a package that includes at least two separate power semiconductorchips connected in parallel to each other, thereby achieving a packagewith a comparatively small total on-state resistance (R_(on)) and,correspondingly, with comparatively small static losses.

Exemplary embodiments of the package disclosed herein are surface-mountdevice (SMD) packages, e.g., SMD-TSC packages. Other embodiments of thepackages are configured in accordance with the through-hole technology,e.g., packages in accordance with other embodiments are based on the SIP(single in-line package) or DIP (dual in-line package) or DIPP (dualin-line pin package) technology. Further exemplary embodiments of thepackage disclosed herein are leadless packages.

In accordance with a first embodiment, a package comprises a packagebody with a package top side, a package footprint side and packagesidewalls, the package sidewalls extending from the package footprintside to the package top side; a plurality of power semiconductor chipselectrically connected in parallel to each other, each powersemiconductor chip having a first load terminal and a second loadterminal and being configured to block a blocking voltage appliedbetween said load terminals and to conduct a chip load current betweensaid load terminals; a lead frame structure for electrically andmechanically coupling the package to a carrier with the packagefootprint side facing to the carrier, the lead frame structurecomprising a plurality of first outside terminals. Each first outsideterminal extends out of the package body for interfacing with thecarrier. Each first load terminal of the plurality of powersemiconductor chips is electrically connected, at least by means of onepackage body internal connection member, to at least two of theplurality of first outside terminals. The package further comprises ahorizontally extending conduction layer at the package top side or atthe package footprint side, wherein the conduction layer is electricallyconnected with each of the second load terminals of the plurality ofpower semiconductor chips.

In accordance with a second embodiment, a system for supplying a loadcurrent to a load is presented. The system comprises a power supply, apower supply path for coupling the power supply to the load; and asystem main switch in the power supply path, wherein the system mainswitch comprises one or more packages in accordance with the firstembodiment, wherein the one or more packages are configured to conductthe load current.

In accordance with a further embodiment, a method of processing apackage is provided. The method includes:

-   -   Providing a package body with a package top side, a package        footprint side and package sidewalls, the package sidewalls        extending from the package footprint side to the package top        side;    -   Arranging a plurality of power semiconductor chips in the        package body and electrically connecting the chips in parallel        to each other, each power semiconductor chip having a first load        terminal and a second load terminal and being configured to        block a blocking voltage applied between said load terminals and        to conduct a chip load current between said load terminals;    -   Providing a lead frame structure for electrically and        mechanically coupling the package to a carrier with the package        footprint side facing to the carrier, the lead frame structure        comprising a plurality of first outside terminals, wherein        -   each first outside terminal extends out of the package body            for interfacing with the carrier;        -   each first load terminal of the plurality of power            semiconductor chips is electrically connected, at least by            means of one package body internal connection member, to at            least two of the plurality of first outside terminals; and    -   Providing a horizontally extending conduction layer at the        package top side or at the package footprint side, wherein the        conduction layer is electrically connected with each of the        second load terminals of the plurality of power semiconductor        chips.

Features of optional further embodiments are defined in the dependentclaims. These features may be combined with each other for forming yetfurther embodiments, if not explicitly stated otherwise.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-B both schematically and exemplarily illustrate a section of aperspective projection of a package in accordance with one or moreembodiments;

FIG. 2 schematically and exemplarily illustrates a section of aperspective projection of a power semiconductor chip in accordance withone or more embodiments;

FIG. 3 schematically and exemplarily illustrates a section of aperspective projection of a package in accordance with one or moreembodiments;

FIG. 4 schematically and exemplarily illustrates a section of ahorizontal projection of a package in accordance with one or moreembodiments;

FIG. 5 schematically and exemplarily illustrates a section of ahorizontal projection of a package in accordance with one or moreembodiments; and

FIG. 6 schematically and exemplarily illustrates a section of a circuitdiagram of a system in accordance with one or more embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof and in which are shown byway of illustration specific embodiments in which the invention may bepracticed.

In this regard, directional terminology, such as “top”, “bottom”,“below”, “front”, “behind”, “back”, “leading”, “trailing”, “above” etc.,may be used with reference to the orientation of the figures beingdescribed. Because parts of embodiments can be positioned in a number ofdifferent orientations, the directional terminology is used for purposesof illustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

Reference will now be made in detail to various embodiments, one or moreexamples of which are illustrated in the figures. Each example isprovided by way of explanation, and is not meant as a limitation of theinvention. For example, features illustrated or described as part of oneembodiment can be used on or in conjunction with other embodiments toyield yet a further embodiment. It is intended that the presentinvention includes such modifications and variations. The examples aredescribed using specific language which should not be construed aslimiting the scope of the appended claims. The drawings are not scaledand are for illustrative purposes only. For clarity, the same elementsor manufacturing steps have been designated by the same references inthe different drawings if not stated otherwise.

The term “horizontal” as used in this specification intends to describean orientation substantially parallel to a horizontal surface of asemiconductor substrate or of a semiconductor structure. This can be forinstance the surface of a semiconductor wafer or a chip. For example,both the (first) lateral direction X and the (second) lateral directionY mentioned below can be horizontal directions, wherein the firstlateral direction X and the second lateral direction Y may beperpendicular to each other.

The term “vertical” as used in this specification intends to describe anorientation which is substantially arranged perpendicular to thehorizontal surface, i.e., parallel to the normal direction of thesurface of the semiconductor wafer/chip. For example, the extensiondirection Z mentioned below may be an extension direction that isperpendicular to both the first lateral direction X and the secondlateral direction Y.

In the context of the present specification, the terms “in ohmiccontact”, “in electric contact”, “in ohmic connection”, and“electrically connected” intend to describe that there is a low ohmicelectric connection or low ohmic current path between two regions,sections, zones, portions or parts of the device described herein.Further, in the context of the present specification, the term “incontact” intends to describe that there is a direct physical connectionbetween two elements of the respective semiconductor device; e.g., atransition between two elements being in contact with each other may notinclude a further intermediate element or the like.

In addition, in the context of the present specification, the term“electric insulation” is used, if not stated otherwise, in the contextof its general valid understanding and thus intends to describe that twoor more components are positioned separately from each other and thatthere is no ohmic connection connecting those components. However,components being electrically insulated from each other may neverthelessbe coupled to each other, for example mechanically coupled and/orcapacitively coupled and/or inductively coupled. To give an example, twoelectrodes of a capacitor may be electrically insulated from each otherand, at the same time, mechanically and capacitively coupled to eachother, e.g., by means of an insulation, e.g., a dielectric.

Specific embodiments described in this specification pertain to, withoutbeing limited thereto, a power semiconductor chip, e.g., a powersemiconductor chip that may be used within a power converter or a powersupply. Thus, in an embodiment, such chip can be configured to carry aload current that is to be fed to a load and/or, respectively, that isprovided by a power source. For example, the chip may comprise one ormore active power semiconductor cells, such as a monolithicallyintegrated diode cell, and/or a monolithically integrated transistorcell, and/or a monolithically integrated IGBT cell, and/or amonolithically integrated RC-IGBT cell, and/or a monolithicallyintegrated MOS Gated Diode (MGD) cell, and/or a monolithicallyintegrated MOSFET cell and/or derivatives thereof. A plurality of suchdiode cells and/or such transistor cells may be integrated in the chip.

The term “power semiconductor chip” as used in this specificationintends to describe a single chip with high voltage blocking and/or highcurrent-carrying capabilities. In other words, such power semiconductorchip is intended for high current, typically in the Ampere range, e.g.,up to 5 or 100 Amperes or even up to 1.000 A and above, and/or voltagestypically above 15 V, more typically up to 40 V, and above, e.g., up toat least 500 V or more than 500 V, e.g. at least 600 V, or even up to2.000 V and above.

For example, the power semiconductor chip described below may be a chipthat is configured to be employed as a power component in a low-,medium- and/or high voltage application.

For example, the term “power semiconductor chip” as used in thisspecification is not directed to logic semiconductor devices that areused for, e.g., storing data, computing data and/or other types ofsemiconductor-based data processing.

FIG. 2 schematically and exemplarily illustrates a section of aperspective projection of a power semiconductor chip 100 in accordancewith one or more embodiments.

The power semiconductor chip 100 has a first load terminal 101 and asecond load terminal 102. The power semiconductor chip 100 is configuredto block a blocking voltage applied between said load terminals 101, 102and to conduct a chip load current between said load terminals 101, 102.

The power semiconductor chip 100 may have been processed, together withother power semiconductor chips, within a semiconductor wafer which hasbeen diced into the individual power semiconductor chips aftercompletion of the wafer processing.

For example, during such wafer processing, the first load terminal 101is formed for each designated chip, e.g., by depositing an electricallyconductive material, e.g. a metal, on a front side of the wafer. Formingthe first load terminals 101 on the front side of the wafer may includeusing a mask. The first load terminals 101 are typically formed afterthe configuration of the semiconductor body 10 is finished.

The second terminal 102 is typically formed on a backside of the wafer,e.g., without a mask but substantially homogeneously along the entireback side. For example, the second load terminal 102 may include abackside metallization.

Hence, the chip 100 can have a vertical configuration, according towhich the first load terminal 101 is arranged at the chip front side andthe second load terminal 102 is arranged at a chip backside. In lateraldirections, e.g., in the lateral directions X and Y and linearcombinations thereof, the chip may be terminated by a chip edge, e.g., aside surface extending in the vertical direction Z.

The semiconductor body 10 is coupled between the first load terminal 101and the second load terminal 102. For example, if a voltage appliedbetween the first load terminal 101 and the second load terminal 102 ispositive (e.g., the electrical potential of the second load terminal 102being greater than the electrical potential of the first load terminal101), the semiconductor body 10 conducts the (forward) load currentbetween the load terminals 101 and 102. If the voltage is negative, thesemiconductor body 10 may be configured to block such voltage andinhibit a flow of the load current between the load terminals 101, 102;i.e., the chip 100 can have a reverse blocking configuration. In anotherembodiment, the chip 100 has a reverse conducting (RC) configuration.

For example, the power semiconductor chip 100 may be a diode, wherein,for example, the first load terminal 101 can be a cathode terminal andthe second load terminal 102 can be an anode terminal.

In another embodiment, the power semiconductor chip 100 can be acontrollable power semiconductor chip, such as a transistor or a gateddiode or a thyristor or a derivative of one of the aforementionedvariants. For example, the power semiconductor chip 100 may comprise acontrol terminal 103, which is typically arranged also at the front sideof the power semiconductor chip 100. In an embodiment, the first loadterminal 101 may hence be a source/emitter terminal, and the second loadterminal 102 may be a drain/collector terminal.

The possible basic configurations of the power semiconductor chip 100(transistor (e.g., MOSFET, IGBT etc.), diode and thyristor) are known tothe skilled person and, hence, it is refrained from explaining these inmore detail. Embodiments described herein are not limited to a specifictype of a power semiconductor chip. For example, the chips may also bedesigned as monolithic bidirectionally blocking and conducting powersemiconductor chips. For example, each of the chips can be a Si-,SiC-MOSFET or a GaN-HEMT (high-electron-mobility transistor).

Further, it shall be noted that the first load terminal 101 could alsobe arranged at the back side of the power semiconductor chip 100, andthat the second load terminal 102 could also be arranged at the frontside of the power semiconductor chip 100.

For example, the chips 100 that are included in the package 200(described below) each have the same MOSFET configuration.

Before being able to be employed within an application, the powersemiconductor chip 100 is usually included within a package that mayallow mechanically mounting and electrically connecting the chip withinthe application, e.g., also for heat distribution purposes. Such packagemay environmentally seal the included power semiconductor chip 100.

FIGS. 1A-B both schematically and exemplarily illustrate a section of aperspective projection of a package 200 in accordance with one or moreembodiments. It will now be referred to both FIG. 1A and FIG. 1B.

The package 200 comprises a package body 20 with a package top side 201,a package footprint side 202 and package sidewalls 203, the packagesidewalls 203 extending from the package footprint side 202 to thepackage top side 201.

The package body 20 can be made of or, respectively, comprise a moldingmass. For example, the package body 20 exhibits a flat configuration,according to which: each of the package top side 201 the packagefootprint side 202 extend substantially horizontally along the first andsecond lateral directions X and Y; the package sidewalls 203 extendsubstantially vertically along the vertical direction Z; and a maximumhorizontal extension of the package footprint side 202 amounts to atleast twice of a maximum vertical extension of the package sidewalls203.

A lead frame structure of the package 100 is configured for electricallyand mechanically coupling the package 200 to a carrier 300 with thepackage footprint side 202 facing to the carrier 300.

The carrier 300 may be a printed circuit-board (PCB) or may be acomponent of a PCB. In another embodiment, the carrier 300 may be aDirect Copper Bond (DCB) substrate, e.g. a ceramic circuit board, or maybe a component of a DCB substrate. In yet another embodiment, thecarrier 300 may also be based on an Insulated Metallic Substrate (IMS).The carrier 300 may be made of an electrically insulating material,e.g., made of a polymer, a PCB laminate, a ceramic, a flame retardant(FR) material (e.g., FR4), a composite epoxy material (CEM), such asCEM1 or CEM3, a Bismaleimide-Triazine resin (BT) material, imide,polyimide, ABF, or made of a combination of the aforementioned exemplarymaterials.

In an embodiment, the package 200 is coupled to the carrier via the leadframe structure of the package 200.

The package 200 encloses a plurality of power semiconductor chips 100electrically connected in parallel to each other, each powersemiconductor chip 100 having a first load terminal 101 and a secondload terminal 102 and being configured to block a blocking voltageapplied between said load terminals 101, 102 and to conduct a chip loadcurrent between said load terminals 101, 102.

The explanation of the power semiconductor chip 100 presented above withrespect to FIG. 2 may equally apply to each power semiconductor chip 100included in the package 200.

In an embodiment, the chips 100 included in the package 200 are equallyconfigured. For example, each chip 100 exhibits the same MOSFETconfiguration.

For example, the chips 100 are sandwiched in between the package topside 201 and the package footprint side 202. The package body 20 mayentirely surround the chips 100 and seal the chips 200 against theenvironment. Further aspects of the arrangement of the chips 100 will bedescribed below.

The lead frame structure of the package 200 may serve as an electricallyconductive interface between the first load terminals 101 of the chips100 (and, if present, the one or more further terminals of the chips(control and/or sense terminals) and other components (not illustrated)that are fixed at the carrier 300. For example, the carrier 300 maycomprise or be provided with other components (not illustrated; forexample, one or more other packages including one or more other chips,and/or a controller, a sensor, a passive component, a load or the like)to which the terminals of the chips 100 are to be coupled via the leadframe structure. A connection between the lead frame structure and theterminals of the chips 100, e.g., the first load terminals 101, may berealized by package internal connection means, and for connecting thechips with other components external of the package 200, the lead framestructure may comprise one or more outside terminals, as will now beexplained in more detail further below.

As used herein, the formulation “electrically connected in parallel toeach other” shall mean that all first load terminals 101 of the chips100 enclosed in the package 200 exhibit the substantially the same firstelectrical potential, and that all second load terminals 102 of theenclosed chips 100 exhibit the substantially the same second electricalpotential. For example, the total load current of the package iscollectively and simultaneously conducted by the plurality of chips 100.Hence, said formulation is not intended to also encompass so-calledanti-parallel connections (e.g., two anti-parallel connected diodes donot simultaneously conduct a load current).

For example, each chip 100 exhibits the same on-state resistance(R_(on)), and the total on-state resistance of the package 200 amountshence to approximately R_(on) divided by the total number of chips 100.

Now referring to both FIGS. 1A-B and 3, the lead frame structure 21comprises a plurality of first outside terminals 2111. Each firstoutside terminal 2111 extends out of the package body 20 for interfacingwith the carrier 300.

Each first load terminal 101 of the plurality of power semiconductorchips 100 is electrically connected, at least by means of one packagebody internal connection member 270, to at least two of the plurality offirst outside terminals 2111.

For example, referring to FIG. 3, the package 200 integrates eight chips100, which are arranged in basically two rows parallel to each other.The lead frame structure 21 comprises eight package body internalconnection members 270.

In an embodiment, each package body internal connection member 270 isterminated by at least two first outside terminals 2111, and eachpackage body internal connection member 270 is electrically connected tothe first load terminals 101 of at least two chips (in the illustratedexample to four chips 100). For example, each end of a respectiveconnection member 270 terminates into at least one first outsideterminal 2111.

For example, as illustrated in FIG. 3, at its ends, each package bodyinternal connection member 270 may join, into a respective first loadterminal bar 211 of the lead frame structure 21, which interfaces to aplurality of the first outside terminals 2111.

Furthermore, in an embodiment, each of the first outside terminals 2111extends out of a either a first one of the package sidewalls 203 of thepackage body 20 or out of a second one of the package sidewalls 203 ofthe package body 20, the first package sidewall and the second packagesidewall being arranged opposite to each other. Further, for each firstload terminal 101 of the plurality of power semiconductor chips 100, atleast one of said at least two first outside terminals 2111 that areprovided for the respective first load terminal 101 extends out of thefirst package sidewall and at least another one of said at least twofirst outside terminals 2111 that are provided for the respective firstload terminal 101 extends out of the second package sidewall.

For example, still referring to FIG. 3 as an example, each package bodyinternal connection member 270 may laterally extend substantially fromthe first package sidewall 203 (e.g., in FIG. 3, the right one) to theopposite second package sidewall 203 (e.g., in FIG. 3, the left one)and, along the course of its lateral extension, establish electricalcontact at least one first load terminal 101 of at least one of thechips 100. For example, along the course of its lateral extension, eachpackage body internal connection member 270 establish electrical contactwith the first load terminals 101 of at least two chips 100.

Thus, in more general terms, in accordance with an embodiment, said atleast two first outside terminals 2111 that are provided for each firstload terminal 101 are electrically connected to each other by means ofsaid at least one package body internal connection member 270 within thepackage body 20.

For example, each package body internal connection member 270 isimplemented as a wire-bond, as a clip or as a ribbon-bond.

The package body internal connection members 270 provide an electricallyconductive path between the first load terminals 101 of the chips 100and the first outside terminals 2111. As explained above, at eachpackage sidewall 203, a subset of the first outside terminals 2111 mayjoin into a respective first load terminal bar 211. Each first loadterminal bar 211 may substantially extend in parallel to the packagesidewall 203 and provide for an interface between the subset of thefirst outside terminals 2111 and one or more of the package internalconnection members 270.

The control terminals 103 (not illustrated in FIG. 3) may be connectedto in a similar manner. For example, the package 200 comprises aplurality of third outside terminals 2131. For example, at each of thefirst and the second package sidewall that are opposite to each other,the package 200 comprises at least one control terminal bar 213 thatextends substantially in parallel to the respective package sidewall203. At each sidewall 203, the third outside terminals 2131 join intothe control terminal 213. Within the package body 20, a plurality ofpackage internal control terminal connection members 275 are providedthat extend from the control terminals bars 213 to the respectivecontrol terminals 103 of the package integrated chips 100. For example,the package 200 includes at least one package internal control terminalconnection member 275 for each chip 100. Moreover, as shown in FIG. 3,e.g., the third outside terminals 2131 extend out of a central portionof the first and second package sidewall (central with respect to thesecond lateral direction Y) with a subset of first outside terminals2111 extending out of the first and second package sidewall on eitherside of the third outside terminals 2131 in the second lateral directionY. That is to say, in the example shown in FIG. 3 the packages comprisesa symmetric pinning with respect to the third outside terminals 2131being arranged in the middle and the first outside terminals 2111 onboth sides thereof. For comparison, the examples illustrated e.g. inFIG. 4 has a symmetric pinning with respect to the first outsideterminals 2111 being arranged in the middle with the third outsideterminals 2131 on both sides thereof. Needless to say, also thearrangement shown in FIG. 3 can be adopted for top side cooling as shownin FIG. 1A as well as for bottom side cooling as shown in FIG. 1B.

For example, each package body internal control terminal connectionmember 275 is implemented as a wire-bond, as a clip or as a ribbon-bond.

Furthermore, as explained above, each control terminal bar 213 mayprovide for an interface between a subset of the third outside terminals2131 and a subset of the package body internal control terminalconnection members 275. Also, as explained above, each first loadterminal bar 211 may provide for an interface between a subset of thefirst outside terminals 2111 and a subset of the package body internalconnection members 270.

Now referring again also to FIGS. 1A-B, the package 200 comprises ahorizontally extending conduction layer 22 at the package top side 201(as illustrated in FIG. 1A) or at the package footprint side 202 (asillustrated in FIG. 1B), wherein the conduction layer 22 is electricallyconnected with each of the second load terminals 102 of the plurality ofpower semiconductor chips 100 that are integrated in the package 200. Itis also possible that horizontally extending conduction layers areprovided at both the package top side 201 and the package footprint side202.

For example, the package 200 may hence exhibit a TSC configuration, asin FIG. 1A, or the package 200 may exhibit a BSC (Bottom Side Cooling orBoard Side Cooling) configuration, as in FIG. 1B.

In both variants, the conduction layer 22 can be monolithic and maylaterally overlap with each of the power semiconductor chips 100, e.g.,in both the first and the second lateral direction X and Y.

For example, as best illustrated in FIG. 1A, the conduction layer 22 isarranged substantially coplanar with the package top side 201; e.g., theconduction layer 22 does substantially not protrude from the package topside 201. The conduction layer 22 can have a horizontal surface areaamounting to at least 50%, to at least 60% or to even more than 80% oreven more than 95% (but to less than 100%) of the total surface area ofthe package top side 201. This surface area may be exposed to theenvironment of the package body 20, i.e., the surface area of theconduction layer 22 is not enclosed within the package body 20, butforms a part of an exterior surface. This may apply analogously for theBSC configuration (cf. FIG. 1B).

The conduction layer 22 may be monolithic and extend continuously, i.e.,as a contiguous electrically conductive surface, so as to entirelyoverlap (laterally/horizontally) which each of chips 100 integrated inthe package 200. For example, every chip 100 is arranged within avertical projection of the horizontal surface of the conduction layer22. This exemplary configuration of the conduction layer 22 may also betrue for the embodiment illustrated in FIG. 3 (where no conduction layer22 is illustrated).

In another embodiment, as shown in FIG. 1B, the conduction layer 22 isarranged at the package footprint side 202 and, hence, the package 200may then exhibit said bottom side cooling (BSC) configuration.

In an embodiment, as illustrated in FIGS. 1A-B and FIG. 3, each of theplurality of first outside terminals 2111 extends out of the packagebody 20 at a respective one of the package sidewalls 203. For example,the first outside terminals 2111 are arranged at two sidewalls 203opposite to each, whereas the first outside terminals 2111 are notarranged at the remaining two sidewalls 203.

Furthermore, as also illustrated in FIGS. 1A-B and FIG. 3, each firstoutside terminal 2111 may be arranged at a vertically centered positionof the respective sidewall 203. For example, this may beneficially allowusing the same package 200 as either BSC or TSC package, depending onthe orientation of the outside terminals 2111; these may hence either beorientated towards the conduction layer 22 (corresponding to a BSCconfiguration) or orientated towards the package top/bottom side 201/202where the conduction layer 22 is not provided, yielding a TSCconfiguration.

The explanation of the optional arrangement of the first outsideterminals 2111 in the preceding paragraph may likewise apply to thearrangement of the third outside terminal 2131, in accordance with anembodiment and as exemplarily illustrated in FIGS. 1A-B and FIG. 3.

In an embodiment, the lead frame structure 21 comprises, irrespective ofthe horizontally extending conduction layer 22, no outside terminal thatextends out of the package body 20 and that is electrically connectedwith one or more the second load terminals 102 of the powersemiconductor chips 100. For example, the first load terminals 101 ofall chips 100 that are integrated in the package 200 are electricallycontacted by a package external entity by means of the first outsideterminals 2111, and the second load terminals 102 of all chips 100 thatare integrated in the package 200 are electrically contacted by apackage external entity by means of the horizontally extendingconduction layer 22, and the control terminals 103 (if present) of allchips 100 that are integrated in the package 200 are electricallycontacted by a package external entity by means of the third outsideterminals 2131. In contrast, there is no outside terminal (like theterminals 2111, 2131) provided for the second load terminals 102.

In an embodiment, each of the power semiconductor chips 100 is arrangedat the same vertical level within the package body 20. Further, eachchip 100 can be arranged in the package body 20 such that its secondload terminal 102 faces to the package footprint side 202 and such thatits first load terminal 101 and its control terminal 103 face to thepackage top side 201.

For example, the package top side 201 has a total horizontal surfacearea of at least 4 cm². For example, each package sidewall 203 mayexhibit a total lateral extension of at least 1 cm, at least 2 cm or atleast 3 cm. An exemplary package dimension is 3.72 cm×4.716 cm.

Further, the package top side 201 can be exposed to the environment ofthe package body (20), such that the horizontal surface area of theconduction layer 22 is not enclosed within the package body 20, butforms a part of an exterior surface. This may apply analogously for theBSC configuration (cf. FIG. 1B).

In an embodiment, each power semiconductor chip 100 integrated in thepackage 200 is configured to block a blocking voltage of at least 500 V.Further, a static ohmic resistance measured, during conduction of thechip load currents, between the horizontally extending conduction layer22 and the plurality of first outside terminals 2111 is less than 5 mOhmor even less than 1.5 mOhm. Such comparatively low resistance isachieved at least by means of the parallel connection of the pluralityof chips 100.

In the following, it is referred to FIG. 4, which schematically andexemplarily illustrates a section of a horizontal projection of thepackage 200 in accordance with one or more embodiments. FIG. 4illustrates a package section approximate to one (e.g., the first)package sidewall 203. The package section approximate to the second(opposite) package sidewall 203 may be configured identically, such thatthe package exhibits a symmetrical design.

As explained above, the lead frame structure may comprise the first loadterminal bar 211 and the plurality of first outside terminals 2111extending out of the package body 20 for interfacing with the carrier300 and being electrically connected with the first load terminals 101of at least some of the plurality of power semiconductor chips 100 bymeans of the first load terminal bar 211 and the package internalconnection members 270. For example, at least one or at least two firstoutside terminals 2111 are provided for each power semiconductor chip100.

If present, for electrical connection of the control terminals 103, thepackage 200 may comprise the least one third outside terminal 2131extending out of the package body 20 for interfacing with the carrier300 and being electrically connected with at least one of the controlterminals 103 of the plurality of power semiconductor chips 100. Asillustrated in FIGS. 1A-B, 3 and 4, there can of course be more than onethird outside terminal 2131; e.g., two third outside terminals 2131.However, since controlling the power semiconductor chips 100 by means ofsupplying a control signal to the control terminals 103 does typicallynot require a high current, a few third outside terminals 2131 may besufficient. For example, one or two third outside terminals 2131 areconnected, within the package body 20, to the control terminals 103 ofthe enclosed power semiconductor chips 100, e.g., as explained above, atleast by means of the package internal control terminal connectionmembers 275.

According to the aforesaid, the first outside terminals 2111 areelectrically insulated from the conduction layer 22. If present, the oneor more third outside terminals 2131 are electrically insulated fromboth the first outside terminals 2111 and the conduction layer 22.

One or more or each of the outside terminals 2111 and 2131 may beconfigured to be electrically and mechanically coupled to the carrier300, e.g., by soldering. Within the present specification, the term“outside” may express that the outside terminals 2111 and 2131 may beconfigured to be electrically contacted by means of components(entities) external of the package body 20.

Further, the outside terminals 2111 and 2131 may be designed as pins, asbest illustrated in FIGS. 1A-B and 3. In another embodiment, e.g., forforming a so-called leadless package, the outside terminals 2111 and2131 of the package 200 are flat planar outside terminals. For example,within the present specification, the term “flat planar” may expressthat the outside terminals 2111 and 2131 each exhibit a respectivesubstantially plane bottom surface that has a size with horizontaldimensions (e.g. along each of the first lateral direction X and thesecond lateral direction Y) at least as great as a vertical dimension ofthe respective outside terminal (e.g. along the vertical direction Z),said plane bottom surface laterally overlapping with the packagefootprint side 202. Thus, the package 200 may be a leadless package,e.g., an SMD leadless package. In another embodiment, the outsideterminals 2111 and 2131 are configured as contact pins (as illustrated)or as contact balls.

In the package body 20, the plurality of power semiconductor chips 100are arranged horizontally adjacent to each other along the first lateraldirection X. For example, in terms the vertical direction Z, each chip100 has the same position. For example, each of the power semiconductorchips 100 is arranged at the same vertical level within the package body20. The chips 100 may be arranged equidistantly, e.g., with distancewithin the range of 0.5 mm to 5.0 mm, along the first lateral directionX being present between each pair of adjacent chips 100.

The first load terminal bars 211 of the lead frame structure 21 may alsoextend along the first lateral direction X so as to allow forsubsequently establish, by means of the package internal connectionmembers 270, electrical contact to the first load terminals 101 of thepower semiconductor chips 100.

The first load terminal bars 211 may be spatially displaced from theplurality of chips 100 along the second lateral direction Y (FIG. 4) orthe first lateral direction (FIG. 3), e.g., by a distance within therange of 0.5 mm to 5.0 mm.

In an embodiment, the first outside terminals 2111 extend away from thefirst load terminal bar 211 (within the package body 20) along the firstor second lateral direction X, Y so as to penetrate the package sidewall203 and reach the exterior of the package 200 where they may interfacewith the carrier 300, as illustrated in FIGS. 1A-B, 3 and 4.

Hence, realization of the parallel connection of the plurality of chips100 may at least partially be accomplished by means of the first loadterminal bars 211 and the package internal connection members 270.

For example, the total lateral extension of each first load terminal bar211 may be at least as great as the total lateral extension of the arrayformed by one or more of chips 100.

As explained above, the package internal control terminal connectionmembers 275, e.g., wire bonds, connect the control terminals 103 of thepower semiconductor chips 100 with the control terminal bars 213. Thecontrol terminal bars 213 may each be spatially displaced from theplurality of chips 100 along the first or second lateral direction X, Y,e.g., by a distance within the range of 0.5 mm to 5.0 mm.

In an embodiment, the third outside terminals 2131 extend away from therespective control terminal bar 213 (within the package body 20) alongthe first or second lateral direction X, Y so as to penetrate thepackage sidewall 203 and reach the exterior of the package 200 wherethey may interface with the carrier 300, as illustrated in FIGS. 1A-B, 3and 4.

As illustrated in FIG. 4, the first load terminal bar 211 and thecontrol terminal bar 213 can be arranged adjacent to each other along asecond lateral direction Y. For example, due to the higher number offirst outside terminals 2111 (as compared to the number of third outsideterminals 2131), it may be appropriate to position the control terminalbar 213 between, with respect to the second lateral direction Y, thearray of chips 100 and the first load terminal bar 211. For example, thepackage internal connection members 275 extend either below or above(with respect to the vertical direction Z) the control terminal bar 213so as to connect to the first load terminal bar 211.

In an embodiment, the first load terminal bar 211 is positioned between,with respect to the first lateral direction X, the two third outsideterminals 2131, as illustrated in FIG. 4.

FIG. 3, by contrast, shows a different approach, according to which, ateach of the two opposite package sidewalls, the control terminal bar 213is arranged between two first load terminal bars 211.

As explained above, the second load terminals 102 are electricallyconnected to the conduction layer 22. For example, the second loadterminals 102 are exclusively electrically connected to the conductionlayer 22, and no outside terminals (like terminals 2111 and 2131) areprovided.

FIG. 5 schematically and exemplarily illustrates a section of ahorizontal projection of the package 200 in accordance with one or morefurther embodiments. Also referring to FIG. 3, for example, theplurality of power semiconductor chips 100 comprises a first subset ofN>2 power semiconductor chips 100 and a second subset of N powersemiconductor chips 100. For example, N equals to two, three, four,five, six, seven, eight, nine, or ten. N may even be greater than ten,e.g., equal to or greater than 12, 14 and so on. The total number ofchips 100 included in the package 200 may hence be equal to 2*N.

FIGS. 3 and 5 illustrate embodiments with N=4

In an embodiment, the N power semiconductor chips 100 of the firstsubset are arranged along a first path 100-A that extends, e.g., in thefirst lateral direction X. Further, the N power semiconductor chips 100of the second subset are arranged along a second path 100-B parallel tothe first path 100-A and horizontally displaced therefrom, e.g., alongthe second lateral direction Y. Also, the N chips 100 of the secondsubset may be arranged in a manner as already explained with respect toFIG. 4. Each of the 2*N chips of the first and the second subset mayhave the same position with regards to the vertical direction Z.

The lead frame structure 21 of the package 200 may comprise at least onefirst load terminal bar 211 for both array of chips 100-A and 100-B, asillustrated in FIG. 3 (where two first load terminal bars 211 areprovided for each path 100-A, 100-B) and in FIG. 5 (where one first loadterminal bar 211 is provided for each path 100-A, 100-B).

The first load terminal bar(s) 211 for the first array of N chips 100-Aextend(s) in parallel to the package sidewall(s) 203, e.g., so as toallow for the package internal connection members 275 to subsequentlyestablish electrical contact with the first load terminals 101 of the Npower semiconductor chips 100 of the first subset, e.g., in a manner asalready explained with respect to FIGS. 3 and 4.

The further first load terminal bar(s) 211 for the N chips 100 of thesecond subset in the second array 100-B also extend(s) in parallel tothe package sidewall(s) 203, e.g., so as to allow for the packageinternal connection members 275 to subsequently establish electricalcontact with the first load terminals 101 of the power semiconductorchips 100 of the second subset, e.g., in a manner as already explainedwith respect to FIGS. 3 and 4.

For example, the first load terminal bar(s) 211 for the N chips 100 ofthe first array 100-A is/are arranged within the package body 20 andbetween the first array 100-A and a first one of the package sidewalls203 or, respectively, an opposite second one of the package sidewalls203. As illustrated, the further first load terminal bar(s) 211 for theN chips 100 of the second array 100-B may also be arranged between thesecond array 100-B and the first one of the package sidewalls 203 or,respectively, the opposite second one of the package sidewalls 203.

For example, as already explained above, the conduction layer 22 is usedto provide, e.g., at the package top side 201, an electrical connectionthe second load terminals 102 of each of the 2*N power semiconductorchips 100. Hence, an external contact can be coupled to the conductionlayer 22 and, within the package body 20, the conduction layer 22 iselectrically connected to the second load terminals 102 of each of the2*N power semiconductor chips 100.

In accordance with the embodiments of FIGS. 1A-B, 3, 4 and 5, theparallel connection of all 2*N power semiconductor chips 100 may beestablished by electrically connecting each of the first outsideterminals 2111 with each other, wherein this electrical connection mayalso occur exterior of the package body 20. Further, the parallelconnection of all 2*N power semiconductor chips 100 may be establishedby electrically connecting each of the third outside terminals 2131 witheach other, wherein this electrical connection may also occur exteriorof the package body 20.

In accordance with the embodiment of FIG. 5, the package 200 furtherincludes the horizontally extending conduction layer 22 at the packagetop side 201. If arranged at the package top side, the horizontallyextending conduction layer 22 can be a top side cooling layer. Hence,the package 200 of FIG. 5 may exhibit a TSC configuration. Thehorizontally extending conduction layer 22 may laterally overlap, alongboth the first and second lateral direction X and Y, with some or all(as illustrated) of the power semiconductor chips 100 included in thepackage 200.

Regarding all embodiments described herein, the power semiconductorchips 100 in the package 200 can be configured to be collectively setinto a respective conducting state, e.g., by means of providing acorresponding control signal at the third outside terminals 2131,wherein the first outside terminals 2111 and the conduction layer 22 areconfigured to conduct at least the sum of the chip load currents duringthe conducting state. For example, during the conducting state, thetotal load current is equally distributed among the power semiconductorchips 100 included in the package 200; e.g., if 2*N power semiconductorchips 100 included in the package 200, during the conducting state, eachchip 100 conducts a share of the total load current I_(total) amountingto approximately I_(total)/(2*N), herein referred to as chip loadcurrent.

The parallel connection of the chips 100 included in the package 200allows achieving a comparatively low total on-state resistance of thechips 100 integrated within package 200. For example, the total on-stateresistance of the chips 100 and the package 200, i.e., the totalon-state resistance of the package 200 that integrates the chips 100that are connected in parallel to each other can be equal to or smaller5 mOhm, or smaller than 2 mOhm, or smaller than 1 mOhm.

Further, regarding all embodiments described herein, the package 200 maynot only include the first outside terminals 2111 but, optionally, oneor more third outside terminals 2131. The total number of the thirdoutside terminals 2131 can be limited, e.g., to eight, four, three, ortwo. In addition, the package 200 may include a further outside terminal(not illustrated), e.g., a sense outside terminal that is electricallyconnected to one or more sense terminals of one or more of the enclosedchips 100, e.g., so as to be able to measure an operating parameter,such as a temperature, a voltage and/or the actual load current.However, it is again emphasized, that, in accordance with one or moreembodiments, there is no other externally contactable electricalconductive member, in particular no outside terminal similar to theterminals 2111 and 2131, connected to the second load terminals 102 thanthe conduction layer 22.

As described above, the lead frame structure 21 of the package 200comprises at least the first load terminal bar(s) 211 and the firstoutside terminals 2111. The lead frame structure 21 is configured tomechanically and electrically couple the package body 20 to the carrier300 (e.g., a printed circuit board (PCB)).

In an embodiment, the lead frame structure 21 is a metallic framestructure; hence, the lead frame structure may constitute a metalcarrier arranged partially in the interior of the package body 20 andpartially external of the package body 20.

In accordance with a further embodiment, a method of processing apackage is provided. The method includes:

-   -   Providing a package body with a package top side, a package        footprint side and package sidewalls, the package sidewalls        extending from the package footprint side to the package top        side;    -   Arranging a plurality of power semiconductor chips in the        package body and electrically connecting the chips in parallel        to each other, each power semiconductor chip having a first load        terminal and a second load terminal and being configured to        block a blocking voltage applied between said load terminals and        to conduct a chip load current between said load terminals;    -   Providing a lead frame structure for electrically and        mechanically coupling the package to a carrier with the package        footprint side facing to the carrier, the lead frame structure        comprising a plurality of first outside terminals, wherein        -   each first outside terminal extends out of the package body            for interfacing with the carrier;        -   each first load terminal of the plurality of power            semiconductor chips is electrically connected, at least by            means of one package body internal connection member, to at            least two of the plurality of first outside terminals; and    -   Providing a horizontally extending conduction layer at the        package top side or at the package footprint side, wherein the        conduction layer is electrically connected with each of the        second load terminals of the plurality of power semiconductor        chips.

Exemplary embodiments of processing method correspond to the embodimentsof the package 200 described above with respect to FIGS. 1A-b to FIG. 5.For example, the processing method may include ensuring that each of thepower semiconductor chips is arranged, within the package body, at thesame vertical level. Hence, the total thickness (e.g., the distancebetween the package top side and the package footprint side) of thepackage does not depend on the total number of chips included in thepackage.

For example, even though the processed package may hence include aplurality of chips electrically connected in parallel to each other,existing package processing platforms may be used. For example, existingdie/wire bond platforms may be employed for forming the embodiments ofthe package 200 described above with respect to FIGS. 1A-B to FIG. 5.

In the following, it will be referred to FIG. 6, which schematically andexemplarily illustrates a section of a circuit diagram of a system 1000in accordance with one or more embodiments.

The system 1000 is configured to supply a load current to a load 500.The load 500 can be constituted by an electric system of a vehicle, forexample. For example, the load may comprise an electric drive of thevehicle, e.g., for driving the vehicle itself or an electric brakeand/or one or more other electric components of the vehicle.

The system 1000 comprises a power supply 400 that provides a powersupply signal at power supply terminals 401, 402. The power supply 400can for example be a DC power supply, e.g., including a batterysupplying a DC voltage between power supply terminals 401 and 402. Thepower supply 400 may alternatively or additionally comprise a(non-illustrated) power semiconductor converter circuit providing thepower supply signal at the power supply terminals 401, 402, e.g., a DCvoltage of at least 100 V.

The system 1000 further comprises a power supply path 600 for couplingthe power supply 400 to the load 500. The power supply path 600 mayinclude one or more of following: one or more cables, one or more wires,one or more connectors, one or more copper lines etc.

A system main switch 700 is arranged in the power supply path 600. Thesystem main switch 700 can be configured to selectively set the powersupply path 600 into a blocking state (i.e., such that the power supplypath 600 is interrupted and no load current can be supplied from thepower supply 400 to the load 500) and a conducting state, during whichthe power supply path 600 is conductive and the load 500 can be suppliedwith the load current generated by the power supply 400. Hence, if thesystem main switch 700 is closed (i.e., ON), the system main switchconducts the load current currently drawn by the load 500.

For example, the system main switch 700 can be a battery main switch.For example, the system main switch 700 is operated at a comparativelylow switching frequency, e.g., of less than 1 Hz. A main switch istypically not operated continuously with a constant switching frequency,but irregularly, e.g., only several times a day (in case of use as abattery main switch in a vehicle, for example).

The system main switch 700 comprises one or more packages 200 inaccordance with one or more embodiments described above. The one or morepackages 200 are configured to conduct the load current supplied to theload 500.

Hence, a beneficial application of the embodiments of the package 200described above may be its use within a main switch, such as a batterymain switch. Such switches typically require very low static losses duelong lasting on-states that may occur (e.g. for several hours or evenfor several days). In contrast, such applications do typically notrequire very low switching losses, since the switching events are ratherrare. Thus, embodiments of the package 200 described above may be usedto replace conventional main switches, such as relays, contactors or thelike.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the respective device inaddition to different orientations than those depicted in the figures.Further, terms such as “first”, “second”, and the like, are also used todescribe various elements, regions, sections, etc. and are also notintended to be limiting. Like terms refer to like elements throughoutthe description.

As used herein, the terms “having”, “containing”, “including”,“comprising”, “exhibiting” and the like are open ended terms thatindicate the presence of stated elements or features, but do notpreclude additional elements or features.

With the above range of variations and applications in mind, it shouldbe understood that the present invention is not limited by the foregoingdescription, nor is it limited by the accompanying drawings. Instead,the present invention is limited only by the following claims and theirlegal equivalents.

1. A package, comprising: a package body with a package top side, apackage footprint side and package sidewalls, the package sidewallsextending from the package footprint side to the package top side; aplurality of power semiconductor chips electrically connected inparallel to each other, each power semiconductor chip having a firstload terminal and a second load terminal and being configured to block ablocking voltage applied between the first and second load terminals andto conduct a chip load current between the first and second loadterminals; a lead frame structure configured to electrically andmechanically couple the package to a carrier with the package footprintside facing the carrier, the lead frame structure comprising a pluralityof first outside terminals, wherein: each first outside terminal extendsout of the package body for interfacing with the carrier; and each firstload terminal of the plurality of power semiconductor chips iselectrically connected, at least by one package body internal connectionmember, to at least two of the plurality of first outside terminals; anda horizontally extending conduction layer at the package top side or atthe package footprint side, wherein the conduction layer is electricallyconnected with each of the second load terminals of the plurality ofpower semiconductor chips.
 2. The package of claim 1, wherein theconduction layer is monolithic and overlaps horizontally with each ofthe power semiconductor chips.
 3. The package of claim 1, wherein eachof the plurality of power semiconductor chips is controllable andcomprises a respective control terminal.
 4. The package of claim 3,wherein the lead frame structure comprises a plurality of controloutside terminals for interfacing with the carrier, and wherein each ofthe plurality of control outside terminals is electrically connectedwith a control terminal of at least one of the plurality of powersemiconductor chips.
 5. The package of claim 3, wherein each powersemiconductor chip has a vertical configuration according to which itsfirst load terminal and its control terminal are arranged at a chipfront side and its second load terminal is arranged at a chip backside,and wherein each power semiconductor chip is arranged in the packagesuch that its chip front side faces the package top side.
 6. The packageof claim 1, wherein each of the power semiconductor chips is arranged ata same vertical level within the package body.
 7. The package of claim1, wherein the lead frame structure comprises, irrespective of thehorizontally extending conduction layer, no outside terminal thatextends out of the package body and that is electrically connected withone or more the second load terminals of the power semiconductor chips.8. The package of claim 1, wherein: each of the first outside terminalsextends out of a either a first one of the package sidewalls of thepackage body or out of a second one of the package sidewalls of thepackage body, the first package sidewall and the second package sidewallbeing arranged opposite to each other; for each first load terminal ofthe plurality of power semiconductor chips, at least one of the at leasttwo first outside terminals that are provided for the respective firstload terminal extends out of the first package sidewall and at leastanother one of the at least two first outside terminals that areprovided for the respective first load terminal extends out of thesecond package sidewall.
 9. The package of claim 8, wherein the at leasttwo first outside terminals that are provided for each first loadterminal are electrically connected to each other by the at least onepackage body internal connection member within the package body.
 10. Thepackage of claim 1, wherein the package top side has a total horizontalsurface area: of at least 4 cm²; and/or that is exposed to theenvironment of the package body, such that the horizontal surface areaof the conduction layer is not enclosed within the package body, butforms a part of an exterior surface.
 11. The package of claim 1, whereinthe horizontally extending conduction layer: is monolithic; and/orlaterally overlaps with each of the power semiconductor chips; and/or isarranged substantially coplanar with the package top side; and/or doesnot laterally protrude from the package top side; and/or has ahorizontal surface area amounting to at least 50%, to at least 60% or tomore than 80%, but to less than 100% of the total horizontal surfacearea of the package top side.
 12. The package of claim 1, wherein eachpower semiconductor chip is configured to block a blocking voltage of atleast 500 V.
 13. The package of claim 1, wherein a static ohmicresistance measured, during conduction of the chip load currents,between the horizontally extending conduction layer and the plurality offirst outside terminals is less than 5 mOhm.
 14. The package of claim 1,wherein each power semiconductor chip has a vertical configurationaccording to which its first load terminal and its control terminal arearranged at a chip front side and its second load terminal is arrangedat a chip backside, and wherein each power semiconductor chip isarranged in the package such that its chip front side faces to thepackage top side.
 15. The package of claim 1, wherein the plurality ofpower semiconductor chips comprises a first subset of N>2 powersemiconductor chips and a second subset of N power semiconductor chips,wherein the power semiconductor chips of the first subset are arrangedalong a first path, and wherein the power semiconductor chips of thesecond subset are arranged along a second path parallel to the firstpath and horizontally displaced therefrom.
 16. The package of claim 1,wherein each of the plurality of first outside terminals extends out ofthe package body at a respective one of the package sidewalls.
 17. Thepackage of claim 16, wherein each first outside terminal is arranged ata vertically centered position of the respective sidewall.
 18. A systemfor supplying a load current to a load, the system comprising: a powersupply; a power supply path configured to couple the power supply to theload; and a system switch in the power supply path, wherein the systemswitch comprises one or more packages of claim 1, wherein the one ormore packages are configured to conduct the load current at leastpartially.